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? 2002 microchip technology inc. ds21460b-page 1 tc7135 features ? low rollover error: 1 count max nonlinearity error: 1 count max reading for 0v input true polarity indication at zero for null detection multiplexed bcd data output ttl-compatible outputs differential input control signals permit interface to uarts and microprocessors blinking display visually indicates overrange condition low input current: 1pa low zero reading drift: 2 v/c auto-ranging supported with overrange and underrange signals available in pdip and surface-mount packages applications precision analog signal processor precision sensor interface high accuracy dc measurements device selection table general description the tc7135 4-1/2 digit a/d converter (adc) offers 50ppm (1 part in 20,000) resolution with a maximum nonlinearity error of 1 count. an auto zero cycle reduces zero error to below 10 v and zero drift to 0.5 v/c. source impedance errors are minimized by a 10pa maximum input current. rollover error is limited to 1 count. microprocessor based measurement systems are sup- ported by busy, strobe and run/hold control sig- nals. remote data acquisition systems with data transfer via uarts are also possible. the additional control pins and multiplexed bcd outputs make the tc7135 the ideal converter for display or microprocessor based measurement systems. functional block diagram part number package temperature range tc7135cli 28-pin plcc 0 cto+70 c TC7135CPI 28-pin pdip 0 cto+70 c tc7135cbu 64-pin pqfp 0 cto+70 c tc7135 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 100k ? analog gnd 100 k ? signal input 0.1 f set v ref = 1v v- ref in analog common int out az in buff out c ref - c ref + -input +input d5 (msd) b1 (lsb) b2 v+ underrange overrange strobe run/hold digtal gnd polarity clock in busy (lsd) d1 d2 d4 (msb) b8 b4 d3 + 5v 1 f 100k ? 1 f 0.47 f v ref in clock input 120kh z ?5v 4-1/2 digit a/d converter
tc7135 ds21460b-page 2 ? 2002 microchip technology inc. package types note: nc = no internal connection. tc7135 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 overrange b4 d3 d2 d1 (lsd) busy clock in polarity digtal gnd underrange b2 (lsb) b1 (msd) d5 v+ +input ? input c ref + c ref - buff out az in int out analog com ref in v- strobe run/hold d4 b8 (msb) 28-pin pdip 28-pin pdip 19 20 21 22 23 24 25 11 10 9 8 7 6 5 clock in run/hold tc7135 az in polarity 12 13 14 15 17 18 (msd) d5 (lsb) b1 b2 b4 (msb) b8 d4 d3 digtal gnd busy d1 (lsd) d2 buff out ref cap ? ref cap+ ? input v+ 4 3 2 1 27 26 28 int out analog com ref in v ? ur or strobe 16 +input 4 3 2 16 15 14 10 9 8 7 6 5 12 11 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tc7135 64-pin pqfp nc int out nc az in nc nc nc c ref + c ref - nc ? input nc +input nc v+ l 32 buff out nc busy d2 d1 63 61 60 59 58 57 56 55 54 53 52 51 50 49 64 nc nc nc nc nc dgnd pol nc clock in 62 nc nc nc nc nc nc overrange underrange nc v- ref in analog com nc nc nc nc nc nc d5 nc nc nc nc d3 nc nc d4 b8 b4 b2 nc b1 nc 13 40 41 42 43 44 45 46 34 35 36 37 38 39 33 48 47 1 run/hold strobe
? 2002 microchip technology inc. ds21460b-page 3 tc7135 1.0 electrical specifications absolute maximum ratings* positive supply voltage..........................................+6v negative supply voltage ....................................... - 9v analog input voltage (pin 9 or 10) .... v+ to v- (note 2) reference input voltage (pin 2) ...................... v+ to v- clock input voltage ........................................ 0v to v+ operating temperature range ............... 0c to +70c storage temperature range ............ ? 65c to +150c package power dissipation; (t a 70c) 28-pin pdip ..................................... 1.14 ? 28-pin plcc .................................... 1.00 ? 64-pin pqfp .....................................1.14 ? *stresses above those listed under "absolute maximum rat- ings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. expo- sure to absolute maximum rating conditions for extended periods may affect device reliability. tc7135 electrical specifications electrical characteristics: t a =+25c,f clock = 120khz, v+ = +5v, v- = -5v, unless otherwise specified (see functional block diagram). symbol parameter min typ max unit test conditions analog display reading with zero volt input -0.0000 0.0000 +0.0000 display reading note 2 and note 3 tc z zero reading temperature coefficient ? 0.5 2 v/c v in =0v,(note4) tc fs full scale temperature coefficient ? ? 5 ppm/c v in =2v, (note4andnote5) nl nonlinearity error ? 0.5 1 count note 6 dnl differential linearity error ? 0.01 ? lsb note 6 display reading in ratiometric operation +0.9996 +0.9999 +1.0000 display reading v in =v ref, (note 2) fse full scale symmetry error (rollover error) ? 0.5 1 count -v in =+v in, (note 7) i in input leakage current ? 1 10 pa note 3 e n noise ? 15 ? v p-p peak-to-peak value not exceeded 95% of time digital i il input low current ? 10 100 av in =0v i ih input high current ? 0.08 10 av in =+5v v ol output low voltage ? 0.2 0.4 v i ol =1.6ma v oh output high voltage; b 1 ,b 2 ,b 4 ,b 8 ,d 1? d 5 busy, polarity, overrange, underrange, strobe 2.4 4.4 5 v i oh =1ma 4.9 4.99 5 v i oh =10 a f clk clock frequency 0 200 1200 khz note 8 note 1: limit input current to under 100 a if input voltages exceed supply voltage. 2: full scale voltage = 2v. 3: v in =0v. 4: 30c t a +70c 5: .external reference temperature coefficient less than 0.01ppm/c. 6: -2v v in +2v. error of reading from best fit straight line. 7: iv in | = 1.9959. 8: specification related to clock frequency range over which the tc7135 correctly performs its various functions. increased errors result at higher operating frequencies.
tc7135 ds21460b-page 4 ? 2002 microchip technology inc. power supply v+ positive supply voltage 4 5 6 v v- negative supply voltage -3 -5 -8 v i+ positive supply current ? 1 3 ma f clk =0hz i- negative supply current ? 0.7 3 ma f clk =0hz pd power dissipation ? 8.5 30 mw f clk =0hz tc7135 electrical specifications (continued) electrical characteristics: t a =+25c,f clock = 120khz, v+ = +5v, v- = -5v, unless otherwise specified (see functional block diagram). symbol parameter min typ max unit test conditions note 1: limit input current to under 100 a if input voltages exceed supply voltage. 2: full scale voltage = 2v. 3: v in =0v. 4: 30c t a +70c 5: .external reference temperature coefficient less than 0.01ppm/c. 6: -2v v in +2v. error of reading from best fit straight line. 7: iv in | = 1.9959. 8: specification related to clock frequency range over which the tc7135 correctly performs its various functions. increased errors result at higher operating frequencies.
? 2002 microchip technology inc. ds21460b-page 5 tc7135 2.0 pin descriptions the description of the pins are listed in table 2-1. table 2-1: pin function table pin number 28-pin pdip symbol description 1 v- negative power supply input. 2 ref in external reference input. 3 analog common reference point for ref in. 4 int out integrator output. integrator capacitor connection. 5 az in auto zero inpt. auto-zero capacitor connection. 6 buff out analog input buffer output. integrator resistor connection. 7c ref - reference capacitor input. reference capacitor negative connection. 8c ref + reference capacitor input. reference capacitor positive connection. 9 -input analog input. analog input negative connection. 10 +input analog input. analog input positive connection. 11 v+ positive power supply input. 12 d5 digit drive output. most significant digit (msd) 13 b1 binary coded decimal (bcd) output. least significant bit (lsb) 14 b2 bcd output. 15 b4 bcd output. 16 b8 bcd output. most significant bit (msb) 17 d4 digit drive output. 18 d3 digit drive output. 19 d2 digit drive output. 20 d1 digit drive output. least significant digit (lsd) 21 busy busy output. at the beginning of the signal-integration phase, busy goes high and remains high until the first clock pulse after the integrator zero crossing. 22 clock in clock input. conversion clock connection. 23 polarity polarity output. a positive input is indicated by a logic high output. the polarity output is valid at the beginning of the reference integrate phase and remains valid until determined during the next conversion. 24 dgnd digital logic reference input. 25 run/hold run / hold input. when at a logic high, conversions are performed continuously. a logic low holds the current data as long as the low condition exists. 26 strobe strobe output. the strobe output pulses low in the center of the digit drive outputs. 27 overrange over range output. a logic high indicates that the analog input exceeds the full scale input range. 28 underrange under range output. a logic high indicates that the analog input is less than 9% of the full scale input range.
tc7135 ds21460b-page 6 ? 2002 microchip technology inc. 3.0 detailed description (all pin designations refer to 28-pin dip) 3.1 dual slope conversion principles the tc7135 is a dual slope, integrating a/d converter. an understanding of the dual slope conversion tech- nique will aid in following the detailed tc7135 operational theory. the conventional dual slope converter measurement cycle has two distinct phases: 1. input signal integration 2. reference voltage integration (de-integration) the input signal being converted is integrated for a fixed time period. time is measured by counting clock pulses. an opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. the reference integration time is directly proportional to the input signal. in a simple dual slope converter, a complete conver- sion requires the integrator output to "ramp-up" and "ramp-down." a simple mathematical equation relates the input sig- nal, reference voltage, and integration time: equation 3-1: for a constant v in : equation 3-2: the dual slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. an inher- ent benefit is noise immunity. noise spikes are inte- grated, or averaged, to zero during the integration periods. integrating adcs are immune to the large conversion errors that plague successive approximation convert- ers in high-noise environments (see figure 3-1). figure 3-1: basic dual slope converter 3.2 tc7135 operational theory the tc7135 incorporates a system zero phase and integrator output voltage zero phase to the normal two- phase dual-slope measurement cycle. reduced sys- tem errors, fewer calibration steps, and a shorter over- range recovery time result. the tc7135 measurement cycle contains four phases: 1. system zero 2. analog input signal integration 3. reference voltage integration 4. integrator output zero internal analog gate status for each phase is shown in figure 3-1. table 3-1: internal analog gate status 1 r int c int t int 0 v in (t)dt = v ref t deint r int c int where: v ref = reference voltage t int = signal integration time (fixed) t deint = reference voltage integration time (variable). v in = v ref t deint t int + - ref voltage analog input signal + - display switch drive control logic integrator output clock counter polarity control phase control v in v ref variable reference integrate time fixed signal integrate time integrator comparator v in 1/2 v ref conversion cycle phase sw i sw ri +sw ri -sw z sw r sw 1 sw iz reference figures system zero closed closed closed figure 3-2 input signal integration closed figure 3-3 reference voltage integration closed * closed figure 3-4 integrator output zero closed closed figure 3-5 *note: assumes a positive polarity input signal. sw ri would be closed for a negative input signal.
? 2002 microchip technology inc. ds21460b-page 7 tc7135 3.2.1 system zero during this phase, errors due to buffer, integrator, and comparator offset voltages are compensated for by charging c az (auto zero capacitor) with a compensat- ing error voltage. with a zero input voltage the integra- tor output will remain at zero. the external input signal is disconnected from the inter- nal circuitry by opening the two sw i switches. the internal input points connect to analog common. the reference capacitor charges to the reference volt- age potential through sw r . a feedback loop, closed around the integrator and comparator, charges the c az capacitor with a voltage to compensate for buffer ampli- fier, integrator, and comparator offset voltages (see figure 3-2). figure 3-2: system zero phase 3.2.2 analog input signal integration the tc7135 integrates the differential voltage between the +input and -input pins. the differential voltage must be within the device common mode range; - 1v from either supply rail, typically. the input signal polar- ity is determined at the end of this phase. seefigure2-3 figure 3-3: input signal integration phase 3.2.3 reference voltage integration the previously-charged reference capacitor is con- nected with the proper polarity to ramp the integrator output back to zero ( see figure 3-4). the digital reading displayed is: equation 3-3: figure 3-4: reference voltage integration cycle 3.2.4 integrator output zero this phase ensures the integrator output is at 0v when the system zero phase is entered. it also ensures that the true system offset voltages are compensated for. this phase normally lasts 100 to 200 clock cycles. if an overrange condition exists, the phase is extended to 6200 clock cycles (see figure 3-5). figure 3-5: integrator output zero phase . + - + - + - +in ref in analog common ? in sw r sw iz sw z sw z integrator switch closed switch open sw ri + comparator to digital section analog input buffer r int c int c ref c sz sw ri - sw i sw z sw ri +sw ri - sw i sw 1 + - + - + - a nalog common ? in integrator switch closed switch open comparator to digital section analog input buffer r int c int c ref c sz sw i +in sw ri + sw ri - ref in sw r sw z sw i sw 1 sw ri +sw ri - sw iz sw z sw z reading = 10,000 [differential input] v ref + - + - + - ref in analog common ? in integrator switch closed switch open comparator to digital section analog input buffer r int c int c ref c sz sw ri + sw ri +sw ri - sw ri - sw i sw i sw 1 sw r sw z sw iz sw z sw z +in + - + - + - + in a nalog common ? in integrator switch closed switch open comparator to digital section analog input buffer c ref sw i sw ri + sw ri - ref in sw r sw z sw i sw ri +sw ri - sw 1 sw iz sw z r int c int c sz sw z
tc7135 ds21460b-page 8 ? 2002 microchip technology inc. 4.0 analog section functional description 4.1 differential inputs the tc7135 operates with differential voltages (+input, pin 10 and -input, pin 9) within the input amplifier common mode range, which extends from 1v below the positive supply to 1v above the negative supply. within this common mode voltage range, an 86db common mode rejection ratio is typical. the integrator output also follows the common mode voltage and must not be allowed to saturate. a worst- case condition exists, for example, when a large posi- tive common mode voltage with a near full scale neg- ative differential input voltage is applied. the negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. for these critical applications, the integrator swing can be reduced to less than the recommended 4v full scale swing, with some loss of accuracy. the integrator output can swing within 0.3v of either supply without loss of linearity. 4.2 analog common input analog common is used as the -input return dur- ing auto zero and de-integrate. if -input is different from analog common, a common mode voltage exists in the system. however, this signal is rejected by the excellent cmrr of the converter. in most applica- tions, ?input will be set at a fixed, known voltage (power supply common, for instance). in this applica- tion, analog common should be tied to the same point, thus removing the common mode voltage from the converter. the reference voltage is referenced to analog common. 4.3 reference voltage input the reference voltage input (ref in) must be a posi- tivevoltagewithrespecttoanalogcommon.a reference voltage circuit is shown in figure 4-1. figure 4-1: using an external reference mcp1525 2.5 v ref v+ 10k 10k v+ ref in analog common analog ground tc7135 1 f
? 2002 microchip technology inc. ds21460b-page 9 tc7135 5.0 digital section functional description the major digital subsystems within the tc7135 are illustrated in figure 5-1, with timing relationships shown in figure 5-2. the multiplexed bcd output data can be displayed on lcd or led displays. the digital section is best described through a discussion of the control signals and data outputs. figure 5-1: digital section functional diagram latch latch latch latch latch counters control logic multiplexer polarity d5 d4 d3 d2 d1 13 b1 14 b2 15 b4 16 b8 polarity ff msb digit drive signal lsb data output 24 22 25 27 28 26 21 dgnd clock in run/ hold overrange strobe busy underrange zero cross detect from analog section
tc7135 ds21460b-page 10 ? 2002 microchip technology inc. figure 5-2: timing diagrams for outputs 5.1 run/hold input when left open, this pin assumes a logic "1" level. with a run/hold = 1, the tc7135 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. when run/hold changes to a logic "0," the measure- ment cycle in progress will be completed, data held and displayed, as long as the logic "0" condition exists. a positive pulse (>300nsec) at run/hold initiates a new measurement cycle. the measurement cycle in progress when run/hold initially assumed the logic "0" state must be completed before the positive pulse can be recognized as a single conversion run command. the new measurement cycle begins with a 10,001- count auto zero phase. at the end of this phase the busy signal goes high. 5.2 strobe output during the measurement cycle, the strobe control line is pulsed low five times. the five low pulses occur in the center of the digit drive signals (d 1 ,d 2 ,d 3 ,d 5 ) (see figure 5-3). d 5 (msd) goes high for 201 counts when the measure- ment cycles end. in the center of the d 5 pulse, 101 clock pulses after the end of the measurement cycle, the first strobe occurs for one half clock pulse. after the d 5 digit strobe, d 4 goes high for 200 clock pulses. the strobe then goes low 100 clock pulses after d 4 goes high. this continues through the d 1 digit drive pulse. the digit drive signals will continue to permit display scanning. strobe pulses are not repeated until a new measurement is completed. the digit drive signals will not continue if the previous signal resulted in an overrange condition. theactivelowstrobe pulses aid bcd data transfer to uarts, processors and external latches. for more information, please refer to application note 784. figure 5-3: strobe signal low five times per conversion integrator output overrange when applicable underrange when applicable system zero 10,001 counts signal integrate 10,000 counts (fixed) reference integrate 20,001 counts (max) full measurement cycle 40,002 counts busy expanded scale below d5 d4 d3 d2 d1 100 counts digit scan strobe auto zero signal integrate reference integrate d5 d4 d3 d2 d1 digit scan for overrange first d5 of system zero and reference integrate one count longer * * * end of conversion d5 (msd) data busy b1 ? b8 strobe d5 d4 d3 d2 d1 d4 data d3 data d2 data d1 (lsd) data d5 data note absence of strobe 201 counts 200 counts 200 counts 200 counts 200 counts 200 counts 200 counts * * delay between busy going low and first strobe pulse is dependent on analo g input. tc835 outputs
? 2002 microchip technology inc. ds21460b-page 11 tc7135 5.3 busy output at the beginning of the signal integration phase, busy goes high and remains high until the first clock pulse after the integrator zero crossing. busy returns to the logic "0" state after the measurement cycle ends in an overrange condition. the internal display latches are loaded during the first clock pulse after busy and are latched at the clock pulse end. the busy signal does not go high at the beginning of the measurement cycle, which starts with the auto zero cycle. 5.4 overrange output if the input signal causes the reference voltage integra- tion time to exceed 20,000 clock pulses, the over- range output is set to a logic "1." the overrange output register is set when busy goes low and is reset at the beginning of the next reference integration phase. 5.5 underrange output if the output count is 9% of full scale or less (-1800 counts), the underrange register bit is set at the end of busy. the bit is set low at the next signal integration phase. 5.6 polarity output a positive input is registered by a logic "1" polarity sig- nal. the polarity bit is valid at the beginning of refer- ence integrate and remains valid until determined during the next conversion. the polarity bit is valid even for a zero reading. signals less than the converter's lsb will have the signal polar- ity determined correctly. this is useful in null applications. 5.7 digit drive outputs digit drive signals are positive-going signals. the scan sequence is d 5 to d 1 . all positive pulses are 200 clock pulses wide, with the exception d 5 , which is 201 clock pulses wide. all five digits are scanned continuously, unless an overrange condition occurs. in an overrange condition, all digit drives are held low from the final strobe pulse until the beginning of the next reference integrate phase. the scanning sequence is then repeated. this provides a blinking visual display indication. 5.8 bcd data outputs the binary coded decimal (bcd) bits b 8 ,b 4 ,b 2 , and b 1 are positive-true logic signals. the data bits become active at the same time as the digit drive signals. in an overrange condition, all data bits are at a logic "0" state.
tc7135 ds21460b-page 12 ? 2002 microchip technology inc. 6.0 typical applications 6.1 component value selection 6.1.1 integrating resistor the integrating resistor r int is determined by the full scale input voltage and the output current of the buffer used to charge the integrator capacitor, c int . both the buffer amplifier and the integrator have a class a output stage, with 100 a of quiescent current. a 20 adrive current gives negligible linearity errors. values of 5 a to 40 a give good results. the exact value of an integrating resistor for a 20 a current is easily calculated. equation 6-1: 6.1.2 integrating capacitor ( c int ) the product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance buildup will not saturate the inte- grator swing (approximately 0.3v from either supply). for 5v supplies and analog common tied to sup- ply ground, a 3.5v to 4v full scale integrator swing is adequate. a 0.10 fto0.47 f is recommended. in general, the value of c int is given by: equation 6-2: a very important characteristic of the integrating capac- itor c int is that it has low dielectric absorption to pre- vent rollover or ratiometric errors. a good test for dielectric absorption is to use the capacitor with the input tied to the reference. this ratiometric condition should read half scale 0.9999, with any deviation probably due to dielectric absorption. polypropylene capacitors give undetectable errors at reasonable cost. polystyrene and polycarbonate capacitors may also be used in less critical applications. 6.1.3 auto zero and reference capacitors the size of the auto zero capacitor has some influence on the noise of the system. a large capacitor reduces the noise. the reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. the dielectric absorption of the reference and auto zero capacitors are only important at power-on or when the circuit is recovering from an overload. smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery. 6.1.4 reference voltage the analog input required to generate a full scale out- put is v in =2v ref . the stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. for this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made. 6.2 conversion timing 6.2.1 line frequency rejection a signal integration period at a multiple of the 60hz line frequency will maximize 60hz "line noise" rejection. a 100khz clock frequency will reject 50hz, 60hz and 400hz noise. this corresponds to five readings per second (see table 6-1 and table 6-2). table 6-1: conversion rate vs. clock frequency r int = full scale voltage 20 a c int = [10,000 x clock period] x i int integrator output voltage swing = (10,000) (clock period) (20 a) integrator output voltage swing oscillator frequency (khz) conversion rate (conv./sec.) 100 2.5 120 3 200 5 300 7.5 400 10 800 20 1200 30
? 2002 microchip technology inc. ds21460b-page 13 tc7135 table 6-2: line frequency rejection vs. clock frequency the conversion rate is easily calculated: equation 6-3: 6.3 high speed operation the maximum conversion rate of most dual slope a/d converters is limited by the frequency response of the comparator. the comparator in this circuit follows the integrator ramp with a 3 secdelay,ataclockfre- quency of 160 khz (6 sec period), half of the first ref- erence integrate clock period is lost in delay. this means that the meter reading will change from 0 to 1 witha50 v input, 1 to 2 with 150 v,2to3at250 v, etc. this transition at midpoint is considered desirable by most users. however, if the clock frequency is increased appreciably above 200khz, the instrument will flash "1" on noise peaks, even when the input is shorted. for many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. since the nonlinearity and noise do not increase substantially with frequency, clock ratesofupto~1mhzmaybeused.forafixedclockfre- quency, the extra count, or counts, caused by compara- tor delay, will be a constant and can be subtracted out digitally. the clock frequency may be extended above 160khz without this error, however, by using a low value resis- tor in series with the integrating capacitor. the effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the refer- ence integrate phase. by careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the compar- ator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. at higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. the minimum clock frequency is established by leak- age on the auto zero and reference capacitors. with most devices, measurement cycles as long as 10 sec- onds give no measurable leakage error. the clock used should be free from significant phase or frequency jitter. several suitable low-cost oscillators are shown in section 6.0, typical applications. the multiplexed output means that if the display takes sig- nificant current from the logic supply, the clock should have good psrr. 6.4 zero crossing flip flop the flip flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half clock pulse have died down. false zero crossings caused by clock pulses are not recognized. of course, the flip flop delays the true zero crossing by up to one count in every instance. if a correction were not made, the display would always be one count too high. there- fore, the counter is disabled for one clock pulse at the beginning of the reference integrate (de-integrate) phase. this one-count delay compensates for the delay of the zero crossing flip flop and allows the correct num- ber to be latched into the display. similarly, a one-count delay at the beginning of auto zero gives an overload display of 0000 instead of 0001. no delay occurs during signal integrate so that true ratiometric readings result. 6.5 generating a negative supply a negative voltage can be generated from the positive supply by using a tc7660 (see figure 6-1). figure 6-1: negative supply voltage generator oscillator frequency (khz) line frequency rejection (hz) 300 60 200 150 120 100 40 33-1/3 250 50 166-2/3 125 100 100 50, 60,400 reading 1/sec = clock frequency (hz) 4000 tc7660 tc7135 11 1 +5v 8 23 (-5v) v+ v ? 24 10 f 5 4 10 f + +
tc7135 ds21460b-page 14 ? 2002 microchip technology inc. figure 6-2: 4-1/2 digit adc with multiplexed common anode led display figure 6-3: rc oscillator circuit figure 6-4: comparator clock circuits 20 19 18 17 12 23 7 8 16 15 14 13 11 2 1 3 9 10 22 6 5 4 6 2 1 7 5 9 ? 15 16 bc 7777 dm7447a blank msd on zero d1 d2 d3 d4 d5 int out az in buff out f in +input ? input analog common v ? ref in pol c ref - b8 b4 b2 b1 +5v +5v x7 0.33 f 200khz + ? a nalog input 1 f 100k ? 1 f 4.7k ? 1 f 1 f ? 5v 100k ? 100k ? d b c a rbi v+ v+ c ref + tc7135 mcp1525 r 2 r 1 f o gates are 74c04 c 1. f o = 1 2c(0.41 r p +0.7r 1 ) r 1 r 2 r 1 +r 2 a. if r 1 =r 2 =r 1 ,f ? 0.55/rc b. if r 2 >> r 1 ,f ? 0.45/r 1 c c. if r 2 << r 1 ,f ? 0.72/r 1 c 2. examples: a. f = 120khz, c = 420pf b. f = 120khz, c = 420pf, r 2 = 50k ? r 1 = 8.93k ? c. f = 120 khz, c = 220 pf, r 2 =5k ? r 1 = 27.3k ? ,r p = r 1 =r 2 10.9 k ? +5v v out 390pf 30k ? 7 8 2 3 16k ? 0.22 f 16k ? 4 1k ? 1 +5v v out 2 3 1 4 7 6 r2 100k ? r2 100k ? r3 50k ? c2 10pf r4 2k ? c1 0.1 f - + lm311 - + lm311 56k ?
? 2002 microchip technology inc. ds21460b-page 15 tc7135 figure 6-5: 4-1/2 digit adc with multiplexed common cathode led display 28 27 26 25 24 23 22 21 9 8 7 6 5 4 3 2 1 ref in analog gnd int out az in buff out c ref + +5v ? 5v ur dgnd polarity or strobe run/hold clk in busy 1 2 3 4 5 6 7 8 9 set v ref = 1v 100 k ? analog gnd 0.33 f 100 k ? 1 f 1 f 47 k ? 150 ? +5v 150 ? 10 11 12 13 14 15 16 17 18 +5 v mc14513 1 f 20 19 18 17 16 15 ? input +input v+ d5 (msd) b1 (lsb) b2 (lsd) d1 d2 d3 d4 b4 (msb) b8 10 11 12 13 14 100 k ? sig in + ? 0.1 f +5v f osc = 200khz c ref - v- tc7135 mcp1525
tc7135 ds21460b-page 16 ? 2002 microchip technology inc. 7.0 packaging information 7.1 package marking information package marking data not available at this time. 7.2 taping forms component taping orientation for 28-pin plcc devices standard reel component orientation for tr suffix device user direction of feed w p package carrier width (w) pitch (p) part per full reel reel size 28-pin plcc 24 mm 16 mm 750 13 in carrier tape, number of components per reel and reel size pin 1 component taping orientation for 64-pin pqfp devices w user direction of feed pin 1 standard reel component orientation for tr suffix device p package carrier width (w) pitch (p) part per full reel reel size 64-pin pqfp 32 mm 24 mm 250 13 in carrier tape, number of components per reel and reel size note: drawing does not represent total number of pins.
? 2002 microchip technology inc. ds21460b-page 17 tc7135 7.3 package dimensions 1.465 (37.21) 1.435 (36.45) .022 (0.56) .015 (0.38) .110 (2.79) .090 (2.29) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .555 (14.10) .530 (13.46) .200 (5.08) .140 (3.56) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .610 (15.49) .590 (14.99) .040 (1.02) .020 (0.51) 28-pin pdip (wide) pin 1 3 ? min. dimensions: inches (mm) 28-pin plcc dimensions: inches (mm) .456 (11.58) .450 (11.43) .495 (12.58) .485 (12.32) .456 (11.58) .450 (11.43) .495 (12.58) .485 (12.32) .050 (1.27) typ. pin 1 .430 (10.92) .390 (9.91) .021 (0.53) .013 (0.33) .032 (0.81) .026 (0.66) .180 (4.57) .165 (4.19) .120 (3.05) .090 (2.29) .020 (0.51) min.
tc7135 ds21460b-page 18 ? 2002 microchip technology inc. 7.3 packaging dimensions (continued) .018 (0.45) .012 (0.30) .031 (0.80) typ. .555 (14.10) .547 (13.90) .555 (14.10) .547 (13.90) .687 (17.45) .667 (16.95) .687 (17.45) .667 (16.95) .010 (0.25) typ. .130 (3.30) max. .120 (3.05) .100 (2.55) .041 (1.03) .031 (0.78) 7 ? max. .009 (0.23) .005 (0.13) pin 1 64-pin pqfp dimensions: inches ( mm )
? 2002 microchip technology inc. ds21460b-page 19 tc7135 sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
tc7135 ds21460b-page 20 ? 2002 microchip technology inc. notes:
? 2002 microchip technology inc. ds21460b-page 21 tc7135 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq ,microid, mplab,pic,picmicro,picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
ds21460b-page 22 ? 2002 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 china - hong kong sar microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 ta iw a n microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom microchip ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 04/20/02 *ds21460b* w orldwide s ales and s ervice

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